Double Data Rate architecture
MRS cycle with address key programs
*CAS latency: CL2 / 2.5/ 3
*Burst length: 2, 4, 8
*Burst type: Sequential & Interleave
2 variations of refresh
*Auto refresh
*Self refresh
Serial Presence Detect support
2 Banks to be operated simultaneously or independently
Package: TSOP/CSP
184 edge connector pads
Data Rate: 400MHz
Clock frequency: 200MHz
Bus width: 64-bit x 2
Data Bandwidth: 6.4GB/s
SSTL-2 interface: 2.6 Voltage +/- 0.1V